High-voltage battery controller alerts

HVBATT alert codes

Showing 351–400 of 424

• HVBATT_a486 — Hv Mon Prefetch Abort Trace HVBATT_a486_HvMonPrefetchAbortTrace CPU Prefetch Abort core backtrace data.
• HVBATT_a487 — Board Power On Reset HVBATT_a487_BoardPowerOnReset The CTRL_MMR reset source register shows that the last MCU reset came from a board power on
• HVBATT_a490 — Hv Mon Data Abort Trace HVBATT_a490_HvMonDataAbortTrace CPU Data Abort core backtrace data.
• HVBATT_a491 — Hv Mon Hard Fault Abort HVBATT_a491_HvMonHardFaultAbort There has been a CPU hard fault exception.
• HVBATT_a492 — Hv Mon Watchdog Violation HVBATT_a492_HvMonWatchdogViolation The processor has experienced a watchdog violation due to an unserviced watchdog. Stack trace values have been dumped from the application.
• HVBATT_a493 — Hv Mon Watchdog Warning HVBATT_a493_HvMonWatchdogWarning A task did not check in on time.
• HVBATT_a494 — Hv Mon Ls Shunt Data Invalid HVBATT_a494_HvMonLsShuntDataInvalid The low-side shunt measurement by HVCON shared memory transfer contains a SPI communication fault or CRC mismatch
• HVBATT_a495 — Hv Mon Ls Shunt Over Current HVBATT_a495_HvMonLsShuntOverCurrent Warns if the low-side shunt current (discharge or charge) is above max current limit.
• HVBATT_a496 — Hv Mon Hs Shunt Data Invalid HVBATT_a496_HvMonHsShuntDataInvalid The high-side shunt measurement by HVCON shared memory transfer contains a SPI communication fault or CRC mismatch
• HVBATT_a497 — Hv Mon Hs Shunt Over Current HVBATT_a497_HvMonHsShuntOverCurrent Warns if the high-side shunt current (discharge or charge) is above max current limit.
• HVBATT_a498 — Hv Mon Bmb Transfer Mia HVBATT_a498_HvMonBmbTransferMia The BMB measurement by HVCON shared memory transfer is not producing data
• HVBATT_a499 — Hv Mon Bmb Voltages Invalid HVBATT_a499_HvMonBmbVoltagesInvalid The BMB brick voltage measurements by HVCON shared memory transfer contains an ISOSPI communication fault or CRC mismatch
• HVBATT_a500 — Hv Mon Bmb Over Voltage HVBATT_a500_HvMonBmbOverVoltage A brick voltage is above the fault voltage limit
• HVBATT_a501 — Hv Mon Bmb Under Voltage HVBATT_a501_HvMonBmbUnderVoltage A brick voltage is above the fault voltage limit
• HVBATT_a502 — Hv Mon Bmb Over Temperature HVBATT_a502_HvMonBmbOverTemperature A module temperature is above the warning temperature limit
• HVBATT_a503 — Pack Ctr Pwr Blocked By Fault HVBATT_a503_PackCtrPwrBlockedByFault HvCon desires for contactor power to be enabled while HvMon has detected a blocking fault.
• HVBATT_a504 — Hv Mon Bmb Temperatures Invalid HVBATT_a504_HvMonBmbTemperaturesInvalid The BMB thermistor measurements by HVCON shared memory transfer contains an ISOSPI communication fault or CRC mismatch
• HVBATT_a505 — Hv Mon High Cpu Load HVBATT_a505_HvMonHighCpuLoad High cpu load was detected across the RTOS tasks
• HVBATT_a506 — Hv Mon High Stack Usage HVBATT_a506_HvMonHighStackUsage High stack usage was detected in one of the RTOS tasks
• HVBATT_a507 — Hv Mon Sw Assertion HVBATT_a507_HvMonSwAssertion There has been a failed software assertion.
• HVBATT_a508 — Hv Mon Sw Assertion Program Counter HVBATT_a508_HvMonSwAssertionProgramCounter The program counter at the location of the failed software assertion.
• HVBATT_a509 — Hv Mon Sw Assertion Link Register HVBATT_a509_HvMonSwAssertionLinkRegister The link register at the location of the failed software assertion.
• HVBATT_a510 — Hv Mon Rtos Stack Overflow Abort HVBATT_a510_HvMonRtosStackOverflowAbort An RTOS task encountered a stack overflow.
• HVBATT_a511 — Hv Mon Bus Fault Abort HVBATT_a511_HvMonBusFaultAbort There has been a CPU bus fault exception.
• HVBATT_a512 — Hv Mon Usage Fault Abort HVBATT_a512_HvMonUsageFaultAbort There has been a CPU usage fault exception.
• HVBATT_a513 — Hv Mon Nmi Abort HVBATT_a513_HvMonNmiAbort There has been a CPU Non-Maskable Interrupt exception.
• HVBATT_a514 — Hv Mon Debug Monitor Abort HVBATT_a514_HvMonDebugMonitorAbort There has been a CPU Debug Monitor exception.
• HVBATT_a515 — Hv Mon Unknown Abort HVBATT_a515_HvMonUnknownAbort The CPU encountered an undefined exception.
• HVBATT_a516 — Hv Mon Abort Debug Data HVBATT_a516_HvMonAbortDebugData Debug data register corresponding to the CPU exception.
• HVBATT_a721 — Hv Proc Ipc Data Channel HVBATT_a721_HvProcIpcDataChannel The processor has experienced an inter-processor communication error amongst its cores.
• HVBATT_a722 — Bp1 D Soc Limiting HVBATT_a722_Bp1DSocLimiting The battery management system (BMS) detects a condition internal to the high voltage (HV) battery that requires the max allowed brick voltage to be limited.
• HVBATT_a723 — Bp2 D Soc Limiting HVBATT_a723_Bp2DSocLimiting The battery management system (BMS) detects a condition internal to the high voltage (HV) battery that requires the max allowed brick voltage to be limited.
• HVBATT_a724 — Bp1 Delta Soc Weak Short HVBATT_a724_Bp1DeltaSocWeakShort A given brick has an alpha signal below the alert alpha threshold.
• HVBATT_a725 — Bp2 Delta Soc Weak Short HVBATT_a725_Bp2DeltaSocWeakShort A given brick has an alpha signal below the alert alpha threshold.
• HVBATT_a728 — Bp1 Bandolier Model Warning HVBATT_a728_Bp1BandolierModelWarning A temperature estimate from the Bandolier Thermal Model for the LS pack is beginning to diverge from the corresponding thermistor measurement. Early warning alert before the model is reset.
• HVBATT_a729 — Bp2 Bandolier Model Warning HVBATT_a729_Bp2BandolierModelWarning A temperature estimate from the Bandolier Thermal Model for the HS pack is beginning to diverge from the corresponding thermistor measurement. Early warning alert before the model is reset.
• HVBATT_a730 — Bp1 Bandolier Model Reset HVBATT_a730_Bp1BandolierModelReset The Bandolier Thermal Model for the HS pack was reset to thermistor temperatures
• HVBATT_a731 — Bp2 Bandolier Model Reset HVBATT_a731_Bp2BandolierModelReset The Bandolier Thermal Model for the LS pack was reset to thermistor temperatures
• HVBATT_a732 — Bp1 Cac Imbalance HVBATT_a732_Bp1CacImbalance The Calculated Amp-hour Capacity (CAC) difference of bricks within a module exceeds the acceptable threshold. This results in reduced battery performance and limits maximum range.
• HVBATT_a733 — Bp2 Cac Imbalance HVBATT_a733_Bp2CacImbalance The Calculated Amp-hour Capacity (CAC) difference of bricks within a module exceeds the acceptable threshold. This results in reduced battery performance and limits maximum range.
• HVBATT_a734 — Bp1 Cac Imbalance Limiting HVBATT_a734_Bp1CacImbalanceLimiting The battery management system (BMS) detects that the calculated Amp-hour capacity (CAC) difference between bricks within a single module exceeds the acceptable threshold, which may reduce battery performance.
• HVBATT_a735 — Bp2 Cac Imbalance Limiting HVBATT_a735_Bp2CacImbalanceLimiting The battery management system (BMS) detects that the calculated Amp-hour capacity (CAC) difference between bricks within a single module exceeds the acceptable threshold, which may reduce battery performance.
• HVBATT_a736 — Bp1 Cac Imbalance Limp HVBATT_a736_Bp1CacImbalanceLimp Calculated Amp-hour Capacity (CAC) difference of bricks within a module exceeds acceptable threshold. This results in reduced battery performance and limits maximum range. Vehicle enters Battery Management System (BMS) limp mode.
• HVBATT_a737 — Bp2 Cac Imbalance Limp HVBATT_a737_Bp2CacImbalanceLimp Calculated Amp-hour Capacity (CAC) difference of bricks within a module exceeds acceptable threshold. This results in reduced battery performance and limits maximum range. Vehicle enters Battery Management System (BMS) limp mode.
• HVBATT_a738 — Bp1 Soc Change HVBATT_a738_Bp1SocChange A State of Charge (SOC) correction of greater than 3% in Battery Subpack 1 occurred during the previous resting period.
• HVBATT_a739 — Bp2 Soc Change HVBATT_a739_Bp2SocChange A State of Charge (SOC) correction of greater than 3% in Battery Subpack 2 occurred during the previous resting period.
• HVBATT_a740 — Bp1 Impedance Deviation HVBATT_a740_Bp1ImpedanceDeviation High impedance was detected on one or more bricks.
• HVBATT_a741 — Bp2 Impedance Deviation HVBATT_a741_Bp2ImpedanceDeviation High impedance was detected on one or more bricks.
• HVBATT_a742 — Vsh Failure HVBATT_a742_VshFailure The battery management system (BMS) has detected a high voltage sense harness (VSH) impedance.
• HVBATT_a743 — Bleed Fet Failure HVBATT_a743_BleedFetFailure A bleed Field-Effect Transistor (FET) on the Battery Management Board (BMB) is not operating as designed. This will prevent the battery from balancing the brick by decreasing the brick voltage.